The current revolution in wireless communications and the need for smaller wireless communications devices have spawned significant efforts directed to the optimization and miniaturization of radio communications electronic devices. Passive components (such as inductors, capacitors and transformers), play a necessary role in the device's operation and thus efforts are directed toward reducing the size and improving the performance and fabrication processes for such components.
Discrete inductors, which play an integral role in the performance of these communications devices, are electromagnetic components comprising a plurality of windings typically enclosing a core constructed of either magnetic material or an insulator. The inductance of an inductor is a measure of the inductor's opposition to changes in the existing current. Use of a magnetic core yields higher inductance values than cores comprised of an insulator, such as air. Typical cores are formed of ferromagnetic material (e.g., iron, cobalt, nickel). These materials comprise a plurality of magnetic domains, and the application of a magnetic field to the core material causes domain alignment and a resulting increase in the material permeability, which in turn increases the inductance. The inductance is also a function of the number of coil turns (specifically, the inductance is proportional to the square of the number of turns), the core size and the core material. Conventional inductors are formed as a helix (also referred to as a solenoidal shape) or a torroid.
With the continual allocation of operational communications frequencies into higher frequency bands, inductor losses increase due to increased eddy current and skin effect losses. To avoid these losses at relatively low operational frequencies, the inductive effect can be simulated by employing certain active devices. But simulated inductors are more difficult to realize at higher frequencies, have a finite dynamic range and inject additional unwanted noise into the operating circuits.
The Q (or quality factor) is an important inductor figure of merit. The Q is a function of the ratio of inductive reactance to inductive resistance, and indicates the sharpness of the inductor's resonance. High Q inductors present a narrow resonant peak when the inductor current is graphed as a function of the input signal frequency, with the peak representing the inductor resonant frequency. High Q inductors are especially important for use in frequency-dependent circuits operating within narrow signal bandwidths. Because the Q value is an inverse function of inductor resistance, it is especially important to minimize the resistance to increase the Q.
Most personal communications devices incorporate integrated circuits fabricated using semiconductor technologies, such as silicon or gallium-arsenide. In the past, integrated planar inductors (including torroidal or spiral shapes) have been employed to achieve compatibility with the silicon-based integrated circuit fabrication processes. However, these planar inductors tend to suffer from high losses and low Q factors at the operational frequencies of the communications devices. These losses and low Q factors are generally attributable to dielectric losses caused by parasitic capacitances and resistive losses due to the use of thin and relatively high resistivity conductors. Also, the magnetic field lines generated during operation of a planar inductor are perpendicular to the major surface of the semiconductor substrate, along which the active devices are formed. These are closed-loop magnetic field lines that enter the material above, laterally adjacent and below the inductor. Field penetration through dielectric materials of the integrated circuit increases the inductive losses thereby lowering the inductor's Q factor. Also, if the inductor is not sufficiently spaced apart from active circuit elements of the integrated circuit, the magnetic fields can induce currents in and affect operation of the active elements.
As integrated circuit active devices grow smaller and operate at higher speeds, the interconnect system can disadvantageously add processing delays to the device signals. In this regard, as the circuit functions demand a greater number of interconnects and as the interconnect cross-section shrinks, conventional interconnect metallization materials, e.g., aluminum, severely limit circuit speeds. Further, the relatively small contact resistance between the aluminum and silicon can be a significant contributor to the total circuit resistance, especially as the number of circuit components and interconnects increases. Finally, as line widths continue to shrink, it becomes increasingly difficult to deposit aluminum within high aspect ratio vias and plugs.
Given theses disadvantages, copper is becoming the material of choice for metallization. It is a better conductor than aluminum (with a resistance of 1.7 micro-ohm cm compared to 3.1 micro-ohm cm for aluminum), is less susceptible to electromigration, can be deposited at lower temperatures (thereby avoiding deleterious effects on the device dopant profiles) and is suitable for use in high aspect ratio applications. Copper interconnects can be formed by chemical vapor deposition, sputtering, electroplating and electrolytic plating.
The damascene process is one technique for forming copper interconnects for integrated circuits. A trench is formed in a surface dielectric layer and copper material is then deposited in the trench. Usually the trench is overfilled, requiring a subsequent chemical/mechanical polishing step to replanarize the dielectric surface. This process of depositing copper in a trench offers superior dimensional control because it reduces dimensional variations relative to variations that are introduced in a typical subtractive metal etch process.
Dual damascene copper processes integrally form both the vertical conductive via portion and the substantially horizontal metal interconnect portion of an interconnect system. The via opening is formed first, followed by formation of an overlying trench. A subsequent metal deposition step fills both the via opening and the trench, forming a complete metal layer. A chemical/mechanical polishing step planarizes the deposited metal with respect to the adjacent dielectric surface.